Course 2: Modeling and Simulation of MOS Analog ICs

Thursday - December 12

8:30-10:00 am
An Overview of the SPICE FET Modeling Infrastructure
Daniel Foty, Gilgamesh Associates
A detailed review of the modeling of FET devices in SPICE. The evolution of
FET models, from the original Level 1 model up through the most recent
developments, such as BSIM3; sample results. Related issues, such as gate
capacitance modeling, systematic process variations, and correlation with
circuit results. Future trends in MOS modeling.

10:30-12:00 am
Benchmarking FET Models for Circuit Design
Daniel Foty, Gilgamesh Associates
The behavior of several popular MOS models. Proactive tests which can be
carried out on foundry MOS models before their use in circuit design.
Methods for determining whether the model shortcomings are caused by
structural deficiencies in the model formulation or by poor parameter
extraction procedures. The difference between digital and analog design
requirements.

1:30-5:00 pm
SPICE: Its Use, Its Limitations and How to Overcome Them
Michael Green, SUNY
The numerical algorithms on which SPICE is based. The interaction of these
algorithms with certain key fundamental aspects of circuits - e.g., circuit
topology and device modeling. In-depth discussion of the following topics:
dc operating point analysis issues, including convergence and stability;
modeling; distortion analysis; transient analysis issues, including
time-step errors and simulation near metastable states; issues regarding
the simulation of RF circuits; alternatives to SPICE.

Friday - December 13

8:30-12:00 am
MOS Modeling Dedicated to Low-Voltage and Low-Current Circuit Design
Christian Enz, EPFL
The basic long-channel static model revisited: pinch-off voltage, modes of
operation, current and transconductance in weak, moderate and strong
inversion. Second-order effects: channel-length modulation, mobility
reduction, velocity saturation, short- and narrow-channel effects,
non-uniform doping. Quasi-static model: charges in weak and strong
inversion. First-order non-quasi-static model. Noise model: thermal noise
in weak and strong inversion, flicker (1/f) noise. Temperature effects. The
EKV model: from hand calculation to computer simulation, pinch-off vs. gate
voltage measurement, parameter extraction, experimental results.

1:30-5:00 pm
Matching of MOS Transistors
Marcel Pelgrom, Philips Research Labs
Basic discussion of the factors affecting the matching properties of MOS
transistors. The two key aspects: deterministic offsets and random offset.
Random offset in the threshold voltage, in the current factor and in the
substrate coefficient. The development over process generations and a
comparison of different processes. The use of practical matching data in
circuit design as illustrated by some examples.

Saturday - December 14

8:30-12:00 am
Interconnect Modeling
Narain Arora, Simplex Solutions, Inc.
An overview of interconnect issues in chip design; interconnect scaling
laws, interconnect as a parasitic element, numerical and analytical methods
of calculating lumped R, C and L of the interconnects. The verification and
calibration of interconnect capacitance models; RC models for full chip
extraction; the impact of process variations on the propagation delay due
to interconnects.

1:30-5:00 pm
Simulation of Substrate/Noise Coupling in Analog and Mixed-Signal ICs
Nishath Verghese, Cadence Design Systems
Overview of the various sources of noise and methods of coupling in ICs
with emphasis on systematic noise coupling mechanisms from switching
voltage and current through the substrate, interconnects and package.
Discussion of substrate coupling and techniques for its analysis.
Modeling the substrate using simple R(C) models. Modeling chip/package
power distribution. Higher-level simulation and modeling of switching
noise in large mixed-signal designs. Application of the modeling/simu-
lation techniques to design and verification of industrial ICs.