Course 2: Modeling and Simulation of MOS Analog ICs

The aim of this course is to examine the limitations of the algorithms used
in SPICE, as well as the existing infrastructure for modeling FETs in
SPICE from the point of view of the circuit designer. To make the most
effective use of foundry MOS models, a circuit designer should be aware of
the strengths and weaknesses of SPICE algorithms, different model types,
and of how parameter extraction affects the final model quality.

The topics covered in the course will include the limitations of SPICE
algorithms and models, MOS modeling dedicated to low-voltage and
low-current circuit design, matching of MOS transistors, interconnect
modeling, behavioral modeling of analog mixed-signal circuits and
simulation techniques for RF circuits and substrate noise coupling.

The speakers are leading experts in the area from high-technology companies
and universities.

Daniel Foty, Gilgamesh Associates
An Overview of the SPICE FET Modeling Infrastructure
Benchmarking FET Models for Circuit Design

Michael Green, SUNY
SPICE: Its Use, Its Limitations and How to Overcome Them

Christian Enz, EPFL
MOS Modeling Dedicated to Low-Voltage/Low-Current Circuit Design

Marcel Pelgrom, Philips Research Labs
Matching of MOS Transistors

Narain Arora, Simplex Solutions, Inc.
Interconnect Modeling

Nishath Verghese, Cadence Design Systems
Simulation of Substrate/Noise Coupling in Analog and Mixed Signal ICs