Short course announcement ENGINEERING SHORT COURSE organized and sponsored by the FABLESS SEMICONDUCTOR ASSOCIATION (FSA) ************************************************************* The EKV MOSFET Model for Analog and Mixed-Mode Circuit Design ************************************************************* A '100% Technical Course'! by Christian Enz, (1,2) Matthias Bucher (1,3) (1) Swiss Federal Institute of Technology, Lausanne (EPFL) (2) Rockwell Semiconductor Systems (3) currently with LSI Logic Corp. Introduction Daniel Foty Gilgamesh Associates DATE: Saturday, November 8, 1997 TIME: 9:30-12:30 and 1:30-4:30 Registration begins: 8:30AM LOCATION: Mentor Graphics, Room B1 108 1001 Ridder Park Dr. San Jose CA 95131 - 2314 COURSE FEE: $200 (payment before Nov. 1) $220 (after Nov. 1) Includes documentation, coffe breaks and lunch. REGISTRATION: Fabless Semiconductor Association Debbie Scoggin, Marketing Director e-mail: debbies@cmputek.net (e-mail Registration form attached below) The FSA gratefully thanks Mentor Graphics for providing the use of its training facilities for this short course. _____________________________________________________________________ ************************************************************* The EKV MOSFET Model for Analog and Mixed Mode Circuit Design ************************************************************* SUMMARY OF CONTENTS * Introduction: General modeling needs in the context of Analog/Mixed Signal and Low Voltage/Low Power Design. * The EPFL-EKV MOSFET model description: A MOSFET model dedicated to Low-Current and Low-Voltage Analog and Mixed-Signal Circuit Design and Simulation. * The EKV MOSFET Model's Structure, Physical Effects included in the Model, Parameters. Practical Information how to handle the model. * Parameter Extraction with the EKV MOSFET Model. Results on current (Deep)-Submicron CMOS Technologies. * Model benchmarking. Circuit Simulation Examples, and Comparison with other MOSFET Models currently in use. * Availablity of the EKV MOSFET Model in Simulators and Parameter Extraction Tools. INTRODUCTION The continuing trend towards low-voltage and low-power deep submicron CMOS design has emphasized new aspects in MOS modeling for analog and mixed analog-digital applications. A clear understanding of the MOS transistor operation at very low current and a correct modeling in the weak and moderate inversion regions (which have been ignored by many designers and model builders for years) have become even more important issues for cost-effective design of high-performance analog and digital integrated circuits. The EPFL-EKV compact MOS transistor model has been developed as a tool that should meet the needs of the circuit designer. Its physical basis ensures excellent modeling of weak-to-strong inversion behavior for current, transconductances and gm/Id ratio. Due to the model's increased availability in circuit simulators (among which ELDO and PSPICE), parameter extraction tools (UTMOST and IC-CAP), the EPFL-EKV model is a powerful design tool, giving the designer insight into device and circuit operation and allowing faster design cycles. COURSE OBJECTIVES The course provides up-to-date information on the EPFL-EKV MOSFET model, dedicated to the design of low-voltage and low-power analog ICs. Key aspects about model formulation and usage, physical effects modeled and meaning of parameters will be addressed. Recent developments of the model, as charge conservation and scaling properties using (deep) submicron CMOS technologies will be discussed. Parameter extraction will be addressed specifically. Furthermore analysis of simple CMOS circuits shows the model's perfor- mance. A comparison to other MOSFET models will be provided and comparative advantages/disadvantages discussed. The model's availability in different dircuit simulators as well as of parameters will be addressed and documen- tation provided. The course is intended for industrial and academic IC designers as well as for engineers involved in MOS characterization. COURSE PROGRAM The short course is scheduled to begin at 9:30 AM and to stop at 4:30 PM. There will be 20 minutes morning and afternoon coffee breaks. Lunch is from 12:30 to 1:30, and is included in the course fee. I. INTRODUCTION. Analog/mixed-signal and low voltage/low power design are rapidly growing in importance. What separates "digital" and "analog" design? MOS model "geneology"/history. What is really needed in MOS models? II. The EKV MOSFET Model: Description. The EKV MOSFET model's hierarchical and coherent structure is described. Basic long-channel static model: pinch-off voltage, modes of operation, current and transconductance in weak, moderate and strong inversion, based on the 'gm/ID' approach. Second-order effects: mobility reduction due to vertical field, velocity saturation. Short- and narrow-channel effects, Non-uniform doping effects. Dynamic modeling: Quasi-static dynamic model for the node charges, charges in weak and strong inversion. Non-quasistatic (NQS) dynamic model. Noise modeling: thermal noise in weak and strong inversion, flicker (1/f) noise. III. The EKV MOSFET Model: Practical Information. Practical information on model usage, and demonstration on Eldo Simulator. Parameter extraction. Practical results and scalability with current (deep) submicron technologies. Circuit simulation with practical examples. Comparison with other mainstream MOS models. Advantages/disadvantages. Model implementation in simulators and parameter availability from foundries. More practical information regarding the use of this MOSFET model. General Discussion and Conclusions. LOCATION Mentor Graphics Room B1 108 1001 Ridder Park Dr. San Jose CA 95131 - 2314 Directions: use 'Brokaw' exit on Interstate-880, heading East. Ridder Park Drive is the first to the left from Brokaw. Mentor Graphics' building is the big white building at the left hand-side. Signs will be provided on-site for the location of the course inside Mentor Graphics' building. REGISTRATION Register by E-mail by returning the form below. Payment must be recieved by Nov. 1 for early registration rate. For VISA payment, call Debbie Scoggin at 972-866-7579. Checks payable to FSA can be mailed to: Debbie Scoggin Fabless Semiconductor Association 13355 Noel Road, Suite 1345 Dallas, TX 75250 COURSE ORGANIZATION Organized by the FSA (Fabless Semiconductor Association). http://www.fsa.org/ The FSA gratefully thanks Mentor Graphics for providing the use of its training facilities for this short course. INSTRUCTORS Daniel Foty is the Founder and President of Gilgamesh Associates, a consulting and research firm specializing in MOS model construction, implementation, and trouble-shooting. He is the author of the best-selling 'MOSFET Modeling with SPICE: Principles and Practice,' which was published by Prentice-Hall. Christan Enz, PhD., Swiss Federal Institute of Technology (EPFL), 1989. Cofounder and former director of Smart Silicon Systems, an IC design company, where he designed low-power and low-noise CMOS ICs. In 1992 he joined the Electronics Laboratories of the EPFL as an Assistant Professor. His technical interests are in device modeling and low-power analog CMOS circuit design. He authored and co-authored more than 50 scientific papers and has contributed to numerous conference presentations and advanced engineering courses. He is currently with Rockwell Semiconductors Corp., Newport Beach CA, and an advisor at EPFL. Matthias Bucher, currently a research assistant at the Electronics Laboratories of the Swiss Federal Institute of Technology (EPFL), where he is preparing a PhD. He is the main developer of the EPFL-EKV model for circuit design and simulation. His interests include MOS transistor modeling for circuit simulation and related characterization methods, with emphasis on short-channel effects and dynamic operation. He is the author of several papers in his field of interest. He is currently staying with LSI Logic Corp., Milpitas CA. ___________________________________________________________________ (send to debbies@cmputek.net) NAME:_____________________________ TITLE:____________________________ COMPANY:__________________________ TEL:______________________________ FAX:______________________________ E-MAIL:___________________________ PAYMENT METHOD:___________________