"MOS Modeling Challenges for Deep Submicron CMOS"

As 0.25um CMOS technology becomes widely available, circuit design
and simulation face numerous challenges.  These challenges also confront
MOS modeling, which provides the key information link between the
circuit designer and the fabrication process.

This presentation will begin by examining the key aspects of deep
submicron CMOS technology, including scaling in theory and in practice,
the short channel limits of FET behavior, and the inability to scale
the threshold voltage due to off-state power constraints.  Implications
for both digital and analog circuit design are considered.  Detailed
aspects of MOS modeling are then described, beginning with a brief
discussion of the shortcomings of older MOS models (such as Level 3 and
BSIM), and continuing with a detailed examination of the two most
commonly-encountered MOS models, HSPICE Level 28 and BSIM3.
Consideration is then given to requirements which must be imposed on
new MOS models, and some emerging models are briefly discussed.  Other
important aspects of MOS modeling, such as the active gate capacitance
and the modeling of process variations, are also considered.  The
presentation concludes with a brief examination of some benchmarking
and pre-screening techniques which a circuit designer can use on an
incoming MOS model parameter deck before employing it for circuit
design.